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general description the max9132/max9134/max9135 high-speed, multi-ple-port, low-voltage differential signaling (lvds) cross- bar switches are specially designed for digital video and camera signal transmission. these switches have a wide bandwidth, supporting data rates up to 840mbps. the max9132 has three input ports and two output ports, the max9134 has three input ports and four out- put ports, and the max9135 has four input ports and three output ports. the digital video or camera signal can go through the switches from an input port to one or multiple output ports. the max9132/max9134/max9135 switch routing is programmable through either an i 2 c interface or a local interconnect network (lin) serial interface. inaddition, the max9134/max9135 provide pins to set switch routing. these pins also set the initial conditions for the i 2 c mode. to generate more input or output ports, these switches can be connected in parallel or incascade. the max9132/max9134/max9135 operate from a +3.3v supply and are specified over the -40? to +105? temperature range. the max9134/max9135 are available in a 32-pin (5mm x 5mm) tqfp package, while the max9132 is available in a 20-pin (6.5mm x 4.4mm) tssop package. the input/output port pins are rated up to ?5kv esd for the iso air-gap discharge model, ?5kv esd for the iec air-gap discharge model, and ?0kv for the esd contact discharge model. all other pins support up to ?kv esd for the human body model. applications digital video in automotivevideo/audio distribution systems camera surveillance systems high-speed digital media routing navigation system displays features ? supports up to 840mbps data rate at each port ? nonactivated ports are in high-impedance statefor easy port expansion ? programmable preemphasis on lvds outputs ? self common-mode biasing on lvds inputs ? three selectable approaches for switch routing: i 2 c interface lin interfaceprogrammable pins (max9134/max9135) ? ?5kv esd protection ? +3.3v supply voltage ? -40? to +105? operating temperature range max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches ________________________________________________________________ maxim integrated products 1 pin configurations 19-4215; rev 2; 4/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available note: devices are specified over the -40? to +105? temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. pin configurations continued at end of data sheet. ordering information part pin-package inputs outputs route control max9132 gup+ 20 tssop-ep* 3 2 i 2 c, lin max9132gup/v+ 20 tssop-ep* 3 2 i 2 c, lin max9134 ghj+ 32 tqfp-ep* 3 4 i 2 c, lin, pins max9135 ghj+ 32 tqfp-ep* 4 3 i 2 c, lin, pins 2019 18 17 16 15 14 13 12 3 4 5 6 7 8 scl/rxdlvdsvdd dout0+ din0- din0+ dvdd pd top view dout0-dout1+ dout1- lvdsgnd din2- din2+ din1- din1+ 1211 9 10 as1/nslpas0 *exposed pad. connect ep to gnd. fs avdd max9132 tssop-ep* sda/txd + downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v avdd = v dvdd = v lvdsvdd = +3.0v to +3.6v, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +4.0v all pins to gnd .............................................-0.3v to v dd + 0.3v short-circuit duration (all outputs).............................continuous continuous power dissipation (t a = +70?) 32-pin tqfp (derate 27.8mw/? above +70?)........2222mw 20-pin tssop (derate 26.5mw/? above +70?) .....2122mw operating temperature range .........................-40? to +105? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection human body model (r d = 1.5k , c s = 100pf) all other pins including scl, sda to gnd .................?kv iec 61000-4-2 (r d = 330 , c s = 150pf) contact discharge (din_, dout_) to gnd ..............................................?0kv air-gap discharge (din_, dout_) to gnd ..............................................?5kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (din_, dout_) to gnd ..............................................?0kv air-gap discharge (din_, dout_) to gnd ..............................................?5kv lead temperature (soldering, 10s) ................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply voltage v dd 3.0 3.6 v max9132 60 80 supply current i avdd , i dvdd , i lvdsvdd outputs switching at20mhz max9134/max9135 86 100 ma single-ended cmos inputs ( pd , fs, rxd) input high level v ih1 2.0 v input low level v il1 0.8 v input high current i in1 v in = 0 to v dd -20 +20 ? single-ended outputs (txd, as1/nslp) output high level v oh v dd - 0.4 v output low level v ol i ol = 4ma 0.4 v 3-level inputs (s5?0, as0, as1) input high level v ih3 2.5 v input low level v il3 0.8 v input open level v io3 measured at the input pins 1.2 1.45 1.9 v input current i l3 , i h3 v il3 = 0v or v ih3 = v dd -20 +20 ? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . 20 tssop-ep junction-to-ambient thermal resistance ( ja ) ........37.7?/w junction-to-case thermal resistance ( jc ) ..................2?/w 32 tqfp-ep junction-to-ambient thermal resistance ( ja ) ...........36?/w junction-to-case thermal resistance ( jc ) ..................4?/w package thermal characteristics (note 1) downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units differential inputs (din_) differential input high threshold v idh v id = v in+ - v in- 100 mv differential input low threshold v idl v id = v in+ - v in- -100 mv common input voltage v com v com = (v in+ - v in- )/2 1.00 1.29 1.60 v input current i in+ , i in- -50 +50 ? differential outputs (dout_) differential output voltage v od 50 ? load, no preemphasis 250 3.65 450 mv change in v od between complementary output states | ? v od |0 1 3 5 m v output common-mode voltage v com 1.125 1.29 1.475 v change in v com between complementary output states | ? v com | 4 013 5m v output short-circuit current i os two output pins connected to gnd -15 -7 ma serial-interface input, output (scl, sda) input high level v ih 0.7 x v dd v input low level v il 0.3 x v dd v h i g h- level outp ut leakag e c ur r ent i leakh open drain with 1k ? pullup to v dd 1 a low-level output v ol i ol = 3ma 0.4 v input capacitance c i 10 pf parameter symbol conditions min typ max units differential signals (dout_) output-to-output skew t sk r l = 100 differential 50 250 ps rise time t r 20% to 80% of the signal swing; r l = 50 differential (r l = 100 double termination), c l = 5pf 0.3 0.4 ns fall time t f 20% to 80% of the signal swing; r l = 50 differential (r l = 100 double termination), c l = 5pf 0.3 0.4 ns duty cycle d input duty cycle 50%; 840mbps clockpattern 45 55 % dc electrical characteristics (continued) (v avdd = v dvdd = v lvdsvdd = +3.0v to +3.6v, t a = -40? to +105? unless otherwise noted. typical values are at v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?.) (note 2) ac electrical characteristics(v avdd = v dvdd = v lvdsvdd = +3.0v to +3.6v, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?.) (notes 3, 4) downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units v id = 200mv, v com = 1.2v, 840mbps clock pattern; input transition time (20% to 80%) =200ps 10 30 ps output peak-to-peak jitter(pr eem p hasi s o n) t j v id = 200mv, v com = 1.2v, 840mbps 2 23 - 1 prbs pattern; input transition time (20% to 80%) = 200ps 85 180 ps propagation delay t d 2n s lvds switchover time t lon s w i tchover ti m e fr om one channel to another 100 ns lv d s w i th p r eem p hasi s am p l i tud e|v odpe | 50 differential (100 double termination) load, 840mbps 335 530 680 mv i 2 c timing clk frequency f scl 400 khz start condition hold time t hd:sta (figure 1) 0.6 ? low period of scl clock t low (figure 1) 1.3 ? high period of scl clock t high (figure 1) 0.6 ? repeated start conditionsetup time t su:sta (figure 1) 0.6 ? data hold time t hd:dat (figure 1) 0 0.9 ? data setup time t su:sta (figure 1) 100 ns setup time for stop condition t su:sto (figure 1) 0.6 ? bus free time t buf (figure 1) 1.3 ? note 2: parameters are 100% production tested at t a = +25?, unless otherwise noted. note 3: i 2 c timing parameters are specified for fast-mode i 2 c. maximum data rate = 400kbps. note 4: parameters are guaranteed by design. ac electrical characteristics (continued)(v avdd = v dvdd = v lvdsvdd = +3.0v to +3.6v, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?.) (notes 3, 4) downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches _______________________________________________________________________________________ 5 80 85 9590 100 105 supply current vs. supply voltage max9132/4/5 toc01 supply voltage (v) supply current (ma) 3.0 3.4 3.2 3.6 preemphasis 840mbps 1010 pattern no preemphasis +105 c +105 c +25 c +25 c -40 c -40 c 75 80 85 90 95 100 105 100 300 200 400 500 600 700 800 supply current vs. data rate max9132/4/5 toc02 data rate (mbps) supply current (ma) preemphasis no preemphasis 1010 pattern +105 c +105 c +25 c +25 c -40 c -40 c 85 95 100 105 110 115 120 125 130 3.0 3.2 3.4 3.6 peak-to-peak jitter vs. supply voltage max9132/4/5 toc03 supply voltage (v) peak-to-peak jitter (ps) 90 preemphasis no preemphasis 840mbps prbs 0 50 150100 200 250 -40 0 20 -20 40 60 80 100 peak-to-peak jitter vs. temperature max9132/4/5 toc04 temperature ( c) peak-to-peak jitter (ps) 840mbps prbs no preemphasis preemphasis 0 50 150100 200 250 100 300 400 200 500 600 700 800 peak-to-peak jitter vs. data rate max9132/4/5 toc05 data rate (mbps) peak-to-peak jitter (ps) prbs pattern no preemphasis preemphasis 53 5152 4950 48 47 46 45 -40 0 20 -20 40 60 80 100 channel-to-channel skew vs. temperature max9132/4/5 toc06 temperature ( c) channel-to-channel skew (ps) 0 5 1510 25 3020 35 100 300 400 200 500 600 700 800 channel-to-channel skew vs. data rate max9132/4/5 toc07 data rate (mbps) channel-to-channel skew (ps) preemphasis 1010 patternv diff = 200mv no preemphasis ov 1ns/div eye diagram max9132/4/5 toc08 150mv/div 200mbps prbs no preemphasis ov 1ns/div eye diagram max9132/4/5 toc09 150mv/div 200mbps prbs with preemphasis typical operating characteristics (v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?, unless otherwise noted.) downloaded from: http:///
pin description pin max9132 tssop max9134 tqfp max9135 tqfp name function 13 13 0 pd p ow er - d ow n inp ut. p d = l ow for p ow er - d ow n. p d = hi g h for p ow er - up w i thout p r eem p hasi s. leave p d op en for p ow er - up w i th p r eem p hasi s on al l outp uts. 23 23 1d v d d digital power supply. bypass dvdd to dgnd with 0.1? and 0.01? capacitors as close as possible to the device. 3 1 1 din0+ port 0 positive input 4 2 2 din0- port 0 negative input 5 3 3 din1+ port 1 positive input 6 4 4 din1- port 1 negative input 5 agnd analog ground 7 6 5 din2+ port 2 positive input 8 7 6 din2- port 2 negative input 7 din3+ port 3 positive input 8 din3- port 3 negative input 989a v d d analog power supply. bypass avdd to agnd with 0.1? and 0.01? capacitors as close as possible to the device. 1 0f s i 2 c and lin interface selection input. fs = low for lin, fs = high for i 2 c. 9 10 s0 routing selection 0 input. see tables 6a and 6b. 10 11 s1 routing selection 1 input. see tables 6a and 6b. 11 12 s2 routing selection 2 input. see tables 6a and 6b. 12 13 s3 routing selection 3 input. see tables 6a and 6b. 11 13 14 as0 3-level i 2 c address selection 0 input (table 3) or lin identifier selection 0 input (table 4) max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v avdd = v dvdd = v lvdsvdd = +3.3v, t a = +25?, unless otherwise noted.) ov 200ps/div eye diagram max9132/4/5 toc10 150mv/div 840mbps prbs no preemphasis ov 200ps/div eye diagram max9132/4/5 toc11 150mv/div 840mbps prbs with preemphasis downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches _______________________________________________________________________________________ 7 pin max9132 tssop max9134 tqfp max9135 tqfp name function 12 14 15 as1/nslp 3-level i 2 c address selection 1 input (in i 2 c mode, table 3). in lin bus mode, it becomes an nslp output, the sleep mode activation pin (activelow) to the lin bus driver. 13 16, 25 19, 24 lvdsgnd lvds ground 17 dout3- port 3 negative output 18 dout3+ port 3 positive output 19 17 dout2- port 2 negative output 20 18 dout2+ port 2 positive output 14 21 20 dout1- port 1 negative output 15 22 21 dout1+ port 1 positive output 16 23 22 dout0- port 0 negative output 17 24 23 dout0+ port 0 positive output 18 15, 26 16, 25 lvdsvdd lvds supply input. bypass lvdsvdd to lvdsgnd with 0.1? and 0.01? capacitors as close as possible to the device. 19 27 26 sda/txd i 2 c data link input/lin tx output. sda/txd becomes sda when in i 2 c mode and txd when in lin mode. 20 28 27 scl/rxd i 2 c clock/lin rx input. scl/rxd becomes scl when in i 2 c mode and rxd when in lin mode. 29 28 s5 routing selection 5 input. see tables 6a and 6b. 30 29 s4 routing selection 4 input. see tables 6a and 6b. 32 dgnd digital ground e p exposed pad. internally connected to gnd. connect to a large groundplane to maximize thermal performance. pin description (continued) downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 8 _______________________________________________________________________________________ dout0+ dout0- max9135 routing control registers pdscl/rxd as0 dout1+ dvdd dgnd avdd agnd lvdsvdd lvdsgnd dout2+ dout1- dout2- din0+ din1+ din0- din1- din2+ din2- din3+ din3- s5 as1/ nslp sda/txd i 2 c/lin interface s4 s3 s2 s1 s0 max9132 routing control registers pdscl/rxd as0 dout0+ dvdd dgnd avdd agnd lvdsvdd lvdsgnd dout1+ dout0- dout1- din0+ din1+ din0- din1- din2+ din2- fs as1/ nslp sda/txd i 2 c/lin interface dout3+ dout3- dout0+ dout0- max9134 routing control registers pdscl/rxd as0 dout1+ dvdd dgnd avdd agnd lvdsvdd lvdsgnd dout2+ dout1- dout2- din0+ din1+ din0- din1- din2+ din2- s5 as1/ nslp sda/txd i 2 c/lin interface s4 s3 s2 s1 s0 functional diagrams downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches _______________________________________________________________________________________ 9 detailed description the max9132/max9134/max9135 high-speed, multi-ple-port, low-voltage differential signaling (lvds) crossbar switches are specially designed for digital video and camera signal transmission. these switches have a wide bandwidth, supporting data rates up to 840mbps. this allows the use of max9132/max9134/ max9135 with lvds serializers/deserializers (serdes) to create a complete video or camera network. the max9132 has three input ports and two output ports, the max9134 has three input ports and four output ports, and the max9135 has four input ports and three output ports. the video or camera signal can go through the switch from an input port to one or multiple output ports. the max9132/max9134/max9135 switch routing is programmable through either an i 2 c interface or a local interconnect network (lin) serial interface. as0and as1 set the slave addresses for either of these modes, allowing several devices on a bus simultane- ously. in addition, the max9134/max9135 provide 3-level pins s[5:0] to set switch routing and the initial conditions for i 2 c mode. to improve the signal integrity, all the lvds outputs feature selectable preemphasis. initial power-up on power-up, all control registers have a value of 0x00.for the max9134/max9135, leaving s[5:0] unconnect- ed, allows control through the lin interface with all out- puts deactivated. otherwise, the switch runs in pin-control mode with s[5:0] controlling the switch rout- ing. the i 2 c is also active while the device is in pin- control mode. successful routing through i 2 c overrides the pin settings. for more details, see the i 2 c interface section. for the max9132, the fs input determineswhich interface is active. register description there are four 1-byte control registers in themax9132/max9134/max9135. these registers control the routing of the switch. table 1 describes the register map for both i 2 c and lin. when the max9132/ max9134/max9135 operate in lin mode, register 0x00acts as an error flag register. its function is described in detail in table 5. in either i 2 c or lin mode, the con- trol registers (0x01, 0x02) program the max9132/max9134/max9135 switch routing control. in addition, these registers can individually activate and deactivate preemphasis for each output port. table 2a describes the routing for the max9132/max9134 and table 2b for the max9135. for i 2 c programming, register 0xff con- trols the activation of routing. sda scl t hd:sta t low t high t r t f t su:dat t su:sta t su:sto t buf t hd:sta t hd:dat start condition stop condition start condition repeated start condition figure 1. i 2 c serial-interface timing details register address (hex) read/ write lin interface description i 2 c description 0x00 r lin status register reserved 0x01 r/w switch control register 1 switch control register 1 0x02 r/w switch control register 2 (max9134/max9135only) switch control register 2 (max9134/max9135only) 0xff w reserved route activation register table 1. register address map downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 10 ______________________________________________________________________________________ register address register bit(s) description value function 0 dout1 preemphasis off d7 dout1 preemphasis 1 dout1 preemphasis on 000 dout1 in high impedance 001 dout1 connected to din1 010 dout1 connected to din0 d[6:4] dout1 routing connection 011 dout1 connected to din2 0 dout0 preemphasis off d3 dout0 preemphasis 1 dout0 preemphasis on 000 dout0 in high impedance 001 dout0 connected to din1 010 dout0 connected to din0 0x01 d[2:0] dout0 routing connection 011 dout0 connected to din2 0 dout3 preemphasis off d7 dout3 preemphasis 1 dout3 preemphasis on 000 dout3 in high impedance 001 dout3 connected to din1 010 dout3 connected to din0 d[6:4] dout3 routing connection 011 dout3 connected to din2 0 dout2 preemphasis off d3 dout2 preemphasis 1 dout2 preemphasis on 000 dout2 in high impedance 001 dout2 connected to din1 010 dout2 connected to din0 0x02 (max9134 only) d[2:0] dout2 routing connection 011 dout2 connected to din2 table 2a. i 2 c/lin switch routing control registers for the max9132/max9134 bit 7. bit 0 ack bit bit 7.bit 0 ack bit 8-bit data as bit 7..bit 0 ack bit 7-bit slave id 0 as addr as address/command byte s p single writesingle read bit 7..bit 0 ack bit bit 7.bit 0 ack bit bit 7.bit 0 ack bit 8-bit data /am bit 7.bit 0 ack bit 7-bit slave id 0as addr as s 7-bit slave id 1as address/command byte s p addr: 8-bit register addresss: 2-wire bus start condition by master p: 2-wire bus stop condition by master as: acknowledge by slave am: acknowledge by master /am: no acknowledge by master figure 2. single-byte write and single-byte read downloaded from: http:///
max9132/max9134/max9135 i 2 c interface the max9132/max9134/max9135 operate as slavesthat send and receive data through i 2 c (see figure 1). the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the slave and generates the scl clock that synchro- nizes the data transfer. the sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on sda. the scl line oper- ates only as an input. a pullup resistor is required onscl if there are multiple masters on the i 2 c interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition sent by a master, followed by the 7-bit slave address plus r/ w bit, a register address byte, a data byte, and finally a stop condition. table 3 showsthe slave address selection by the as0 and as1 pins. data format for writing to the slave a write to the max9132/max9134/max9135 comprisesthe transmission of the slave address with the r/ w bit set to 0, followed by at least 1 byte of information. thefirst byte of information is the command byte. the com- mand byte determines which registers of the max9132/max9134/max9135 are to be written by the next byte, if received. if a stop condition is detected after the command byte is received, the max9132/ max9134/max9135 take no further action beyond stor- ing the command byte. any bytes that are received after the command byte are data bytes. the first data byte goes into the internal register of the crossbar switch selected by the command byte (figure 2). if multiple data bytes are transmitted before a stop con- dition is detected, these bytes are generally stored in subsequent max9132/max9134/max9135 internal reg- isters because the command byte address generally autoincrements (table 1). programmable, high-speed, multiple input/output lvds crossbar switches ______________________________________________________________________________________ 11 register address register bit(s) description value function 0 dout1 preemphasis off d7 dout1 preemphasis 1 dout1 preemphasis on 000 dout1 not connected 001 dout1 connected to din1 010 dout1 connected to din0 011 dout1 connected to din2 d[6:4] dout1 routing connection 100 dout1 connected to din3 0 dout0 preemphasis off d3 dout0 preemphasis 1 dout0 preemphasis on 000 dout0 not connected 001 dout0 connected to din1 010 dout0 connected to din0 011 dout0 connected to din2 0x01 d[2:0] dout0 routing connection 100 dout0 connected to din3 d[7:4] reserved 0000 set these bits to 0000 0 dout2 preemphasis off d3 dout2 preemphasis 1 dout2 preemphasis on 000 dout2 not connected 001 dout2 connected to din1 010 dout2 connected to din0 011 dout2 connected to din2 0x02 d[2:0] dout2 routing connection 100 dout2 connected to din3 table 2b. i 2 c switch routing control registers for the max9135 downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 12 ______________________________________________________________________________________ data format for reading from the slave the max9132/max9134/max9135 are read using thedevices?internally stored command bytes as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer does not autoincrement after each data byte is read. initiate a read by writing the command byte to the proper slave address (figure 2), then send the device? slave address with the r/ w bit set to 1. the slave now responds with the contents of the requested register(figure 2). lin interface the lin interface is a low-speed, low-cost interface usedin slow control signal traffic in automotive applications. this device is the slave node in the lin bus cluster and is designed based on the lin rev. 1.3 specification. the lin master sends data to the max9132/max9134/ max9135 lsb first, up to a maximum data rate of 20kbps. the lin slave node waits for the synchronization pulse, then synchronizes itself to the pulse. the node must then read the identifier and send/receive data bytes to the master, setting the error flag register when neces- sary. the lin interface uses the same routing function of the switch control registers (0x01, 0x02) as the i 2 c inter- frame slot frame response space inter- frame space response header break sync protected indentifier transmitted from master transmitted from a master or slave *n = 2 for writeand 4 for read data 1 data 2 data n* checksum figure 3. lin bus signal format read format write format 0x00 0x01 0x01 data 1 data 2 data 1 data 2 data 3 data 4 0x02 0x02 0xff figure 4. lin write and read data frame pin address as0 as1 a[7:5] a4 a3 a2 a1 a0 address (hex) low low 101 0 0 0 0 r/ w 0xa0 low open 101 0 0 0 1 r/ w 0xa2 low high 101 0 0 1 0 r/ w 0xa4 open low 101 0 0 1 1 r/ w 0xa6 open open 101 0 1 0 0 r/ w 0xa8 open high 101 0 1 0 1 r/ w 0xaa high low 101 0 1 1 0 r/ w 0xac high open 101 0 1 1 1 r/ w 0xae high high 101 1 0 0 0 r/ w 0xb0 table 3. i 2 c slave addresses downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches ______________________________________________________________________________________ 13 face. the routing action takes place after correct check-sum verification. the lin status register (0x00) holds the error flags for the lin transceiver. for a write, the master writes 2 bytes of data to the registers (0x01, 0x02). for a read, the slave outputs the contents of registers 0x00, 0x01, and 0x02, along with the stuffing byte at a constant value (0xff). in either mode, the checksum follows at the end of the data bytes. figure 3 shows the write and read signal frame format. figure 4 shows the lin write and read data frame. lin-protected identifier the lin bus uses the 8-bit protected identifier (pid) toaddress the slave nodes. two parity bits (msbs) along with 6 id bits (lsbs) make up the pid field. table 4 defines the sets of the identifiers for the write/read operations of the lin slave node. as0 selects the iden- tifiers. as1/nslp becomes the nslp output for activat- ing the lin driver chip (max13020). lin error handling register 0x00 contains the error flags found in the linsignal by the slave note (table 5). a successful lin read resets register 0x00. pin control by s[5:0] (max9134/max9135) for the max9134/max9135, the routing can be con-trolled by the hardware pins (s[5:0]). if the i 2 c register 0xff is not written by 0xff, then chip routing is deter-mined by s[5:0]. also, these pins set the initial power- up routing condition of the chip. table 6a gives the details of the routing control for the max9134. table 6b gives the details of the routing control for the max9135. once the i 2 c register 0xff is written by 0xff, the i 2 c registers 0x01 and 0x02 take over the routing and thepin (s[5:0]) setting is ignored. after the i 2 c routing takes place, the pin setting can be changed withoutaffecting the routing. the new pin setting takes effect if the pd pin or the chip supply is toggled. usually, once i 2 c controls the routing, there is no value in using the pin routing. applications information 3-level inputs the max9132/max9134/max9135 use several 3-levelinputs to control the device. use three-state logic to realize the 3-level logic using digital control. alternatively, if a high-impedance output is unavailable, apply a voltage of v dd /2 to realize the midlevel high- impedance state. write id read id as0 id[5:0] pid field id[5:0] pid field low 0x08 0x08 0x27 0xe7 open 0x0a 0xca 0x29 0xe9 high 0x1c 0x9c 0x2b 0x2b table 4. lin identifiers for write and read operations register bit(s) description function d[7:5] reserved reserved d4 sync sync pulse widths outside the given tolerances detected d3 transmit value read on rxd different from value transmitted on txd during a read d2 checksum checksum sent during a write does not match the expected checksum d1 parity id parity bit does not match expected parity d0 frame message frame did not complete within the maximum allowed time table 5. register 0x00 error flag mapping for lin max9132max9134 max9135 v bat max13020 v dd inhtxd rxd nslp linbus txd 5k 5k 5k rxdnslp nwake lin figure 5. connecting the max9132/max9134/max9135 to the max13020 downloaded from: http:///
max9132/max9134/max9135 interface selection using s[5:0] (max9134/max9135) s[5:0] determine which interface controls themax9134/max9135. leave s[5:0] unconnected or set to a midlevel state to enable the lin interface. other settings to s[5:0] set the switch routing according to tables 6a (max9134) and 6b (max9135). the i 2 c inter- face is active when the max9132/max9134/max9135are not in lin interface mode. writing to an i 2 c register overrides the s[5:0] settings. interface selection using fs (max9132 only) the fs input selects the interface for the max9132. setfs low for lin interface control and fs high for i 2 c interface. the max9132 powers up with all lvds out-puts unconnected for either mode. interfacing the max9132/max9134/max9135 to the lin bus the max9132/max9134/max9135 interface to the linbus through the max13020 lin transceivers. this device translates the +12v to +42v lin bus signal down programmable, high-speed, multiple input/output lvds crossbar switches 14 ______________________________________________________________________________________ port s5 s4 s3 s2 s1 s0 connection description 0 dout0 connected to din0 open dout0 connected to din1 x 1 dout0 connected to din2 0 dout1 connected to din0 open dout1 connected to din1 0x x x 1 x dout1 connected to din2 both dout0 and dout1 outputs are on 0 dout0 connected to din0 open dout0 connected to din1 xx x 0 1 dout0 connected to din2 dout1 is not connected, dout0 is on 0 dout1 connected to din0 open dout1 connected to din1 1 x x x open 1 dout1 connected to din2 dout0 is not connected, dout1 is on dout0, dout1 1x x x 1 x dout0 and dout1 in high impedance both dout0 and dout1 are not connected 0 dout2 connected to din0 open dout2 connected to din1 x 1 dout2 connected to din2 0 dout3 connected to din0 open dout3 connected to din1 x0 1 x xx dout3 connected to din2 both dout2 and dout3 outputs are on 0 dout2 connected to din0 open dout2 connected to din1 0 1 xx dout2 connected to din2 dout3 is not connected, dout2 is on 0 dout3 connected to din0 open dout3 connected to din1 x1 open 1 xx dout3 connected to din2 dout2 is not connected, dout3 is on dout2, dout3 x11xxx dout2 and dout3 in high impedance both dout2 and dout3 are not connected table 6a. switch routing control pin setting for the max9134 x = don? care. downloaded from: http:///
to the +3.3v logic level. figure 5 shows the circuit thatinterfaces the crossbar switches to the lin bus. waking up the lin bus driver at power-up, the max9132/max9134/max9135 leavenslp low, keeping the lin bus driver in sleep mode. when the lin driver receives a wake-up signal (figure 6) from the lin bus, the driver pulls rxd low. when the max9132/max9134/max9135 detect a falling edge on rxd, the device pulls nslp high waking up the lin dri- ver. the max9132/max9134/max9135 then enable the txd pin. putting the lin bus driver into sleep mode there are two conditions under which the max9132/max9134/max9135 put the lin driver to sleep: line activity timeout and receiving a sleep command. the first condition arises if there is inactivity on the lin bus for more than 3s. the second condition requires send-ing the data 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff using the identifier 0x3c to the device. if any of the two conditions happen, the device disables txd and drives nslp low. this puts the lin driver into sleep mode. multiple max9132/max9134/max9135 for port expansion the max9132/max9134/max9135 high-impedanceoutputs allow the attachment of several parts in parallel. figure 7 shows example connection schemes to realize larger crossbar connections. lvds output preemphasis the max9132/max9134/max9135 feature a preem-phasis mode where extra current is added to the output and causes the amplitude to increase by 50% at the transition point. preemphasis helps to get a faster tran- sition, better eye diagram, and improved signal integri- ty (see the typical operating characteristics ). during data transition, the switch injects additional current fora short period, typically 400ps. leave pd open or apply a midlevel voltage (v dd /2) to enable preemphasis on all lvds outputs. set pd high to set preemphasis through the i 2 c or lin interfaces. preemphasis in this mode is initially not on. power-down set pd low to enable power-down mode. the registers retain their values and the device resumes operationfrom the same mode upon power-up. max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches ______________________________________________________________________________________ 15 > 30 s rxd figure 6. lin bus wake-up signal x = don? care. port s5 s4 s3 s2 s1 s0 connection description 0 0 dout0 connected to din0 0 open dout0 connected to din1 0 xxxx 1 dout0 connected to din2 1 0 dout0 connected to din3 dout0 1 xxxx open dout0 in high impedance s5 and s0 determine dout0 connection 0 0 dout1 connected to din0 0 open dout1 connected to din1 0 xx 1 dout1 connected to din2 1 0 dout1 connected to din3 dout1 x 1 xx open x dout1 in high impedance s4 and s1 determine dout1 connection 0 0 dout2 connected to din0 0 open dout2 connected to din1 0 1 dout2 connected to din2 1 0 dout2 connected to din3 dout2 x x 1 open xx dout2 in high impedance s3 and s2 determine dout2 connection table 6b. switch routing control pin setting for the max9135 downloaded from: http:///
max9132/max9134/max9135 input/output termination terminate lvds inputs/outputs through 100 ? differen- tial termination, or use an equivalent thevenin termina-tion. terminate both inputs/outputs and use identical terminations on each for the lowest output-to-output skew. power-supply bypassing adequate power-supply bypassing is necessary tomaximize the performance and noise immunity. bypass each supply to their respective grounds with high- frequency surface-mount 0.01? ceramic capacitors as close as possible to the device. use multiple bypass vias for connection to minimize inductance. board layout separate the i 2 c/lin signals and lvds signals to pre- vent crosstalk. when possible, use a four-layer pcbwith separate layers for power, ground, lvds, and digi- tal signals. layout pcb traces for 100 ? differential characteristic impedance. the trace dimensionsdepend on the type of trace used (microstrip or stripline). route the pcb traces for an lvds channel (there are two conductors per lvds channel) in parallel to main- tain the differential characteristic impedance. place the 100 ? (typ) termination resistor at both ends of the lvds driver and receiver. avoid vias. if vias must beused, use only one pair per lvds channel and place the via for each line at the same point along the length of the pcb traces. this way, any reflections occur at the same time. do not make vias into test points for automated test equipment. make the pcb traces thatmake up a differential pair the same length to avoid skew within the differential pair. cables and connectors interconnect for lvds typically has a differentialimpedance of 100 ? . use cables and connectors that have matched differential impedance to minimizeimpedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality com- pared to ribbon cable and tend to generate less emi due to magnetic-field-canceling effects. balanced cables pick up noise as common mode that is rejected by the lvds receiver. add a 0.1? capacitor in series with each output for ac-coupling. choosing pullup resistors i 2 c requires pullup resistors to provide a logic-high level to data and clock lines. there are tradeoffsbetween power dissipation and speed, and a compro- mise must be made in choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for a datarate up to 400kbps (see the i 2 c interface section for details). to meet the rise time requirement, choose thepullup resistors so that the rise time t r = 0.85r pullup x c bus < 300ns. if the transition time becomes too slow, the setup and hold times may not be met and wave-forms are not recognized. programmable, high-speed, multiple input/output lvds crossbar switches 16 ______________________________________________________________________________________ 3 x 8 switch 6 x 4 switch dout1 dout2 dout3 dout4 din1 din2 din3 max9134 dout1 dout2 dout3 dout4 din1 din2 din3 max9134 dout1 dout2 dout3 dout4 din1 din2 din3 max9134 dout1 dout2 dout3 dout4 din1 din2 din3 max9134 figure 7. topologies for port expansion downloaded from: http:///
exposed pad the tqfp and tssop packages used for themax9132/max9134/max9135 have exposed pads on the bottom. the exposed pad is internally connected to ground. connect the exposed pad to ground using a landing pad large enough to accommodate the entire exposed pad. add vias from the exposed pad? land area to a copper polygon on the other side of the pcb to provide lower thermal impedance from the device to the ambient air. esd protection the max9132/max9134/max9135 esd tolerance israted for iec 61000-4-2, human body model, and iso 10605 standards. iec 61000-4-2 and iso 10605 speci- fy esd tolerance for electronic systems. the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 ? (figure 8). for iec 61000-4-2, the lvds outputs are rated for ?0kv contact discharge and?5kv air-gap discharge. the human body model discharge components are c s = 100pf and r d = 1.5k ? (figure 9). for the human body model, all pins are rated for ?kv contact discharge. the iso 10605discharge components are c s = 330pf and r d = 2k ? (figure 10). for iso 10605, the lvds outputs are ratedfor ?0kv contact and ?5kv air-gap discharge. max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches ______________________________________________________________________________________ 17 c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 ? figure 8. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m ? r d 1.5k ? c s 100pf figure 9. human body esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k ? c s 330pf figure 10. iso 10605 contact discharge esd test circuit downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches 18 ______________________________________________________________________________________ dvddagnd avdd 0.1 f 0.1 f scl/rxdsda/txd as1/nslp as0 lvdsgnd lvdsvdd lvds inputs lvds outputs connect s[5:0] according to desired initial routing dout0+ dout0- dout1+ dout1- dout2+ dout2- dout3+ dout3- max9134 100 ? 3 100 ? 4 din0+ din0- din1+ din1- din2+ din2- v dd r pu r pu to i 2 c master s0 s1 s2 s3 s4 s5 v dd typical application circuit downloaded from: http:///
max9132/max9134/max9135 programmable, high-speed, multiple input/output lvds crossbar switches ______________________________________________________________________________________ 19 pin configurations (continued) max9134 tqfp-ep* top view 2930 28 27 1211 13 14 1 + 24567 23 24 22 20 19 18 s5s4 s3s2 s1 s0 3 21 31 10 32 9 26 15 25 16 8 17 scl/rxd lvdsvdd dout0+ din0- din0+ dvdd pd dout0-dout1+ dout1- dout2+ dout2- dout3+ dout3- lvdsgnd lvdsvdd lvdsgnd din2- din2+ din1- din1+ as1/nslpas0 *exposed pad. connect ep to gnd. avdd agnd sda/txd max9135 tqfp-ep* top view 2930 28 27 1211 13 14 1 + 24567 23 24 22 20 19 18 s5s4 s3s2 s1 s0 3 21 31 10 32 9 26 15 25 16 8 17 scl/rxd lvdsvdd dout0+ lvdsgnd din0- din0+ dgnd dvdd pd dout0-dout1+ dout1- lvdsgnd dout2+ dout2- lvdsvdd din2- din2+ din1- din1+ as1/nslpas0 avdd *exposed pad. connect ep to gnd. din3- din3+ sda/txd chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 tssop-ep u20e+1 21-0108 90-0114 32 tqfp-ep h32e+6 21-0079 90-0326 downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 20 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. programmable, high-speed, multiple input/output lvds crossbar switches max9132/max9134/max9135 revision history revision number revision date description pages changed 0 7/08 initial release 1 2/11 updated pin control by s[5:0] (max9134/max9135) and interface selection using fs (max9132 only) sections 13, 14 2 4/11 added automotive part (max9132) to ordering information 1 downloaded from: http:///

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